[H-GEN] Tag RAM and lots of memory

[Martin Pool]

On Thu, 25 Sep 1997, David Jericho wrote:

> But on a more serious note, I remember Andrae some while back talking
> about cache flushes when the cpu does a context switch (I think I have
> that right). 

<speculation q=0.5/That's not necessarily so, but most (?) processors, or
at least pentiums, flush the cache (write out/mark invalid) and blow the
pipeline on executing a jump instruction.  This is more because of the
difficulty of implementing pipelined jumps than because it's intrinsically
necessary to maintain consistency.  Pentiums are such a kludge, compared
to a real RISC thing./

> Come to think of it, I don't know how SMP handles those style of
> conditions, and obviously data races could occur...

For every cache line, each process keeps track of whether it is shared,
dirty, clean, or invalid wrt the other processors.  (There's an acronym
something like SMEG... I forget the exact words.)  IIRC, this is carried
out by watching a shared bus to see which addresses are being read or
written by other processors. 

---
Martin

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