[H-GEN] Tag RAM and lots of memory

[Byron Ellacott]

On Mon, 29 Sep 1997, Martin Pool wrote:

> <speculation q=0.5/That's not necessarily so, but most (?) processors, or
> at least pentiums, flush the cache (write out/mark invalid) and blow the
> pipeline on executing a jump instruction.  This is more because of the
> difficulty of implementing pipelined jumps than because it's intrinsically
> necessary to maintain consistency.  Pentiums are such a kludge, compared
> to a real RISC thing./
not sure about pentium (yeah, kludge :) but your generic RISC processor
usually does not kill off the cache on a jump.  Rather, it predicts where
a branch will go, and conditionally executes along that path - if it's
wrong, it discards those results (effectively clearing the pipeline, I
suppose) - some chips (eg sun) will execute the following instruction
while deciding whether or not the branch will be taken, and let the
compiler figure out what to put there.  Some imaginary chips (ie DLX) know
where the branch will go during the decode stage, and so know which
instruction will be executed next before it becomes a problem.  PowerPC
(iirc) replaces the jump instruction itself with the target instruction,
hence getting 0 cycle branch instructions :)


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